There are many integrated circuit (IC) chip, or die, packaging technologies. A number of advanced IC packages include a plurality of IC chips in a stack, which reduce the footprint of the IC chips to improve device density within a given platform (e.g., mobile device, computer, automobile). FIG. 1A illustrates a plan view of a conventional stacked-chip assembly 101. FIG. 1B illustrates a cross-sectional view of stacked-chip assembly 101. As shown, IC chip 111 is stacked over IC chip 110, IC chip 112 is further stacked over IC chip 111, and IC chip 113 is further stacked over IC chip 112. Between each IC chip is a die attach material 140 (e.g., paste or film). To accommodate electrical connection (e.g., power, signal, ground) by wire bonds, stacked chips may be laterally offset or displaced in one or more dimensions relative to an underlying/overlying chip. For example, chip 111 is laterally offset in the x-dimension from an edge of chip 110. Similarly, chip 112 is laterally offset in the x-dimension from an edge of chip 111. Such an IC chip stack requires a footprint that is a function of both the chip size and the cumulative chip offset required for the wire bonds. For example, in FIG. 1B, the stack footprint is a function of both the chip length Lc and offset length Lo. As such, staggering the chips increases package size.
As further shown in FIGS. 1A and 1B, wire bonds may be waterfalled from a top most chip (e.g., 113) to successively lower chips until landing on a package substrate 105. Such waterfalled wire bonds are typical in applications where the chips in the stack are the same and various pads on each chip may be powered, grounded, or signaled concurrently with corresponding pads on another chip. Such an architecture is common for a NAND flash memory chip, which often accommodate metal features on one or two sides of the chip (e.g., opposite edges laterally separated in the x-dimension in FIG. 1A, 1B). In addition to the offset increasing package footprint, package substrate 105 increases the z-thickness of assembly 101, and all increases the cost of the package assembly.
Heat generated by the stacked chips during operation of assembly 101 is another issue. For example, heat generated by chip 110 may need to conduct through chip 111, 112, and 113 to reach a heat sink disposed over the chip stack (e.g., landed on chip 113). The bulk material composition (e.g., silicon) often has a relatively low thermal conductivity, making it difficult to adequately cool chips within a stacked-chip assembly.